Gate Induced Drain Leakage ((GIDL)) current is one of the main leakage current components in Silicon on Insulator (SOI) MOSFET structure and plays an important role in the data retention time of DRAM cells. (GIDL) can dominate the drain leakage current at zero bias and will limit the scalability of the structure for low power applications. In this paper we propose a novel technique for reducing (GIDL) and hence off-state current in the nanoscale single gate SOI MOSFET structure. The proposed structure employs asymmetric gate oxide thickness, which can reduce (GIDL) current, and hence Ioff current to about 98% in comparison with the symmetric gate oxide thickness structure, without sacrificing the driving current and losing gate control over the channel. This technique is very simple in the fabrication point of view in CMOS technology.

In this research, we investigate the ambipolar current in germanene nanoribbon tunneling field effect transistor (GeNR-TFET) using combination of density functional theory (DFT) and non-equilibrium Green’ s function method (NEGF). We propose two different methods to reduce the ambipolar current in the GeNR-TFET: using overlapped gate metal to cover part of the drain side and the other idea is to decrease the doping density in the drain side. The results show that by extension of the metal gate on the drain region, the hole current from the drain to channel reduces and it is possible to reduce this current more by using longer overlapping length. Also, results prove that by decreasing the doping density in the drain side compared with the source region, the ambipolar current declines. We obtain that by mixing two proposed ways, the ambipolar current can significantly be reduced. Suppression of this ambipolar current is an important challenge in digital circuit design.

Silicon on insulator junctionless field effect transistor (SOI-JLFET) includes a single type doping at the same level in the source, channel, and drain regions. Therefore, its fabrication process is easier than inversion mode SOI-FET. However, SOI-JLFET suffers from high subthreshold slope (SS) as well as high leakage current. As a result, the SOI-JLFET device has limitation for high speed and low power applications. For the first time in this study, use of the auxiliary gate in the drain region of the SOI-JLFET has been proposed to improve the both SS and leakage current parameters. The proposed structure is called "SOI-JLFET Aug". The optimal selection for the auxiliary gate work function and its length, has improved the both SS and ION/IOFF ratio parameters, as compared to Regular SOI-JLFET. Simulation results show that, SOI-JLFET Aug with 20nm channel length exhibits the SS~71mV/dec and ION/IOFF~1013. SS and ON-state to OFF-state current (ION/IOFF) ratio of SOI-JLFET Aug are improved by 14% and three orders of magnitudes, respectively, as compared to the Regular SOI-JLFET. The SOI-JLEFT Aug could be good candidate for digital applications.

Scaling the channel length leads to the increased leakage current of double gate junctionless field effect transistor (DGJL-FET) and, as a result, the increased power consumption in OFF-state. The present paper proposes a new structure for reducing the leakage current in DGJL-FET, which is called modified DGJL-FET. In this structure, the channel doping under the gate is the same as the drain and source doping but higher than the mid-channel doping. The simulation results indicated that reducing the thickness of the doped layer under the gate, D, resulted in the reduced OFF-state current. For the proposed device with 10 nm channel length, the OFF-state current is less than that in the regular DGJL-FET by two orders of magnitude. Performance of the regular DGJL-FET and modified DGL-FET for different channel lengths is compared based on the IOFF/ION ratio, sub-threshold slope (SS), and intrinsic gate delay. For modified DGJL-FET, the mid-channel doping and Dare considered as additional parameters for improving the device’s performance in nanometer regime. The simulation results indicated that in the proposed device with channel length of 15 nm, values of SS and IOFF/ION ratio are improved compared to the regular DGJL-FET by 14% and 106 orders of magnitude, respectively.

In this paper, the short channel effects of different gate configurations and geometry parameters of carbon nanotube (CNT) field-effect transistors with doped source and drain extensions are investigated. The simulation is based on the self-consistent solution of the three-dimensional Poisson equation and Schrödinger equation with open boundary conditions, within the nonequilibrium Green’s function formalism. Simulation results show that double gate structure offers quasi-ideal subthreshold slope and drain induced barrier lowering even for the rather thick oxide (5nm). Then, the investigation of electrical characteristics of double gate carbon nanotube field-effect transistor (DG-CNTFET) shows that as the CNT normalized density or CNT diameter increases, the current in the on-state increases as well. Also, the off-state current in DG-CNTFET decreases with increasing drain voltage. Furthermore, in the negative gate voltages, for a large drain voltage, increasing in drain current due to band to band tunneling requires a larger negative gate voltage, and for low drain voltage, resonant states appear.

A new structure named as source/drain sides-double recessed gate with N-buried layer in the channel (SDS-DRG) silicon carbide (SiC) based metal semiconductor field effect transistor (MESFET) is presented in this study. Important parameters such as short channel effect, maximum DC trans-conductance, drain current and breakdown voltage of the proposed structure are simulated and compared with those of the source side-double recessed gate (SS-DRG) and drain side-double recessed gate (DS-DRG) 4H-SiC MESFETs. Our simulation results reveal that reducing the channel thickness under the gate at the SDS-DRG structure improves the maximum DC trans-conductance and reduces the short channel effects compared to SS-DRG and DS-DRG structures. Reducing the channel thickness under the gate at the drain side of the SDS-DRG structure is used to enhance the breakdown voltage in comparison with the SS-DRG structure. Also, N-buried layer with larger doping concentration in the SDS-DRG structure improves the saturated drain current compared to SS-DRG and DS-DRG structures.‏

This paper is intended to investigate the impact of structural parameters (in particular: body thickness (TBody), Source/Drain Length (LS /LD) and gate oxide thickness (TOX)) on the electrical characteristics of nanoscale Double Gate SOI MOSFET (DG SOI MOSFET) in subthreshold regime. It will be shown that a reduction in Ls /Ld doesn’t have a profound effect on both on-current and Drain Induced Barrier Lowering Effect (DIBL); however it increases the effective Gate Capacitance (CGeff) significantly. A decrease in Tbody results in an increase in CGeff and a decrease in potential barrier height while ION is reduced.This investigation also proves that as TOX is increased, CGeff is decreased. A decline in TOX reduces ION while it drastically increases ION /IOFF ratio.