In this paper, single-phase dynamic COMPARATOR was improved based on adding a clocked NMOS auxiliary latch at its output and two clocked NMOS transistors at its internal nodes. Using clocked NMOS latch and transistors increased the speed of COMPARATOR, without increasing the loading effect and kick-back noise on its previous and next stages. The advantage of the proposed COMPARATOR rather than the conventional COMPARATOR was higher speed with precence same power dissipations. To demonstrate the mention specifications, proposed and conventional COMPARATORs were analyzed and simulated at 2-GS/s sampling rate in 0. 18-μ m CMOS process. In this case, the outputs of proposed COMPARATOR were determined almost 18-ps (%9) faster than the outputs of conventional COMPARATOR. Also, to compare the performances of proposed and conventional COMPARATORs in flash ADCs, two 4-bits flash ADCs, using proposed and conventional COMPARATORs in their comparison chains blocks, were designed and simulated at 2-GS/s. In this case, the FOM of ADCs with the proposed and conventional COMPARATORs at nyquist rate input frequency achieved 0. 61-pJ/conv. step and 0. 72-pJ/conv. step, respectively. Corresponding, the ENOB of ADCs achieved 3. 74-Bit and 3. 45-Bit, respectively. In addition, the power dissipations of COMPARATORs array of ADCs with proposed and conventional COMPARATORs were 4. 23-mW and 4. 09-mW, respectively. Also, the power dissipations of two flash ADCs, without the power dissipations of their COMPARATORs array, were 11. 70-mW and 12. 03-mW, respectively.

In this paper we have presented a new design of fault tolerant COMPARATOR with a fault free hot spare. The aim of this design is to achieve a low overhead of time and area in fault tolerant COMPARATORs. We have used hot standby technique to normal operation of the system without interrupting and dynamic recovery method in fault detection and correction. The circuit is divided to smaller modules for ease of testing and one hot spare is used for reconfiguration. Complexity, time and area overhead of designed fault tolerant COMPARATOR are more effective in compared recent methods.

In this paper, a new dynamic circuit is proposed to reduce power consumption of tag COMPARATORs. To reduce the power consumption in the proposed dynamic circuit, NMOS transistors are used to precharge the dynamic node. In this way, voltage swing on the dynamic node is decreased and hence the power consumption is reduced. Simulation of wide fan-in OR gates and 40-bit tag COMPARATORs are done using HSPICE simulator in a 90nm CMOS technology model. Simulation results exhibit 42% power reduction and 1. 68× noise-immunity improvement at the same delay compared to the conventional dynamic circuit for 32-bit OR gates. Moreover, simulation results demonstrate 52% and 16% reduction in the power consumption and delay of the proposed tag COMPARATOR, respectively, at the same noise immunity compared to the conventional one.

Background and Objectives: Residue number system (RNS) is considered as a prominent candidate for high-speed arithmetic applications due to its limited carry propagation, fault tolerance, and parallelism in “Addition”, “Subtraction”, and “Multiplication” operations. Whereas, “Comparison”, “Division”, “Scaling”, “Overflow Detection” and “Sign Detection” are considered as complicated operations in residue number systems, which have also received a surge of attention in a multitude of publications. Efficient realization of COMPARATORs facilitates other hard-to-implement operations and extends the spectrum of RNS applications. Such COMPARATORs can substitute the straightforward method (i.e. converting the comparison operands to binary and comparing them with wide word binary COMPARATORs) to compare RNS numbers. Methods: Dynamic Range Partitioning (DRP) method has shown advantages for comparing unsigned RNS numbers in the 3-moduli sets {2^n,2^n±1} and {2^n,2^n-〖1,2〗^(n+1)-1}, in comparison with other methods. In this paper, we employed DRP components and designed a unified unit that detects the sign of operands and also compares numbers, for the 5-moduli set γ={2^2n,2^n±1,2^n±3}. This unit can be used for comparison of signed and also unsigned RNS numbers in the moduli set γ.Results: Synthesized comparison results reveal 47% (54%) speed-up, 35% (32%) less area consumption, 25% (24%) lower power dissipation, and 60% (65%) less energy for n=8 (16) in comparison to the straightforward signed COMPARATOR. Conclusion: According to the results of this study, DRP method for sign detection and comparison operations outperforms other methods in different moduli sets including 5-moduli set γ={2^2n,2^n±1,2^n±3}.

In this paper, dynamic COMPARATORs structure, by employing two methods for power consumption reduction with applications in low-power high-speed analog-to-digital converters, have been presented. The proposed COMPARATORs have low consumption thanks to power reduction methods. They have the ability for adjusting the offset. The COMPARATORs consume 14. 3 and 24 μ W at 100 MHz, which is equal to 3. 7 and 11. 8 fJ. The COMPARATORs are designed and simulated in 180 nm CMOS. Layouts occupy 210 and 240 μ m2, respectively.

In this paper, a photonic crystal structure for comparing two bits has been proposed. This structure includes four resonant rings and some nonlinear rods. The nonlinear rods used inside the resonant rings were made of a doped glass whose linear and nonlinear refractive indices are 1. 4 and 10-14 m2/W, respectively. Using Kerr effect, optical waves are guided toward the correct output ports. In this study, plane wave expansion and finite difference time domain methods were used for calculation of photonic bandgap and simulation of optical wave propagation, respectively. The size of the proposed structure is 1585 μ m2 which is more compact than the previous works. Furthermore, the obtained maximum delay time is about 2 ps that is proper to highspeed processing. The normalized output power margins for logic 0 and 1 are calculated as 25% and 71%, respectively. According to the obtained results, this structure can be used for optical integrated circuits.

The performance of an Analog/Digital (A/D) converter, various aspects like general architecture of the converter, architecture of the building blocks or design of the blocks can be improved. The COMPARATOR block is a fundamental block in data converters. Due to contradicting design purposes, circuit constraints and necessities, design of COMPARATORs and obtaining best circuit performance are complicated and challenging. Such challenges in circuit design necessitate presenting approaches which not only satisfy all the objectives but also, they are cost effective in terms of time and cost. One of the approaches which has recently attracted attentions is the heuristic algorithms based intelligent Methods. Inclined Planes system Optimization algorithm (IPO) is a novel heuristic algorithm inspired by dynamic movement of the objects on frictionless inclined planes. But despite its remarkable ability for exploration and exploitation of the search space, its standard model has complex relationships with many structural parameters that often confuse the user in choosing the effective values for them. In this paper, IPO algorithm is simplified to present a heuristic algorithm (called SIPO) and its efficiency in optimization of 10 standard benchmarks has been evaluated. Then, a multi-objective version of the proposed algorithm (called MOSIPO) for design and optimization of double tail COMPARATOR is presented and its efficiency in optimization of double tail COMPARATOR has been evaluated and compared with popular multi-objective intelligent methods. The results clearly demonstrate the improved performance and superiority of SIPO and MOSIPO compared to the other methods.

In this paper a new implementation of CMOS ripple COMPARATOR cell using the Gate-Diffusion Input (GDI) technique is presented. The proposed design using this technique allows for the reduction of power consumption, propagation delay, and the area of digital circuits while maintaining low complexity of logical design. The performance comparison with standard CMOS and GDI logic design techniques is presented. These methods are compared with respect to the number of devices, PDP, and power dissipation. Simulation results confirm that the proposed cell can work at low supply voltage and dissipates low power.

This paper presents a time-domain COMPARATOR with low supply voltage and low power consumption for using in circuits that COMPARATOR’s input common-mode voltages swing is 0 to half supply voltage. To design the time-domain COMPARATOR, a delay element with a very high delay-voltage gain is proposed. The purpose of designing this COMPARATOR is to achieve high delay-voltage gain, which leads to an increase in the accuracy of the COMPARATOR, as well as a significant reduction in power consumption and occupied area compared to conventional time-domain COMPARATORs. This time-domain COMPARATOR utilizes subthreshold concept and also uses the bulk-voltage of transistor as a COMPARATOR input. The proposed COMPARATOR is simulated in 0.18µm TSMC technology at 1V supply voltage, which according to the intended application, the supply voltage can be reduced to about 0.4V. The simulation results show that with supply voltage of 1V the proposed COMPARATOR consumes 250nW at the clock frequency of 2.5MHz. The figure of merit of 0.1µW/MHz indicates the high performance of the proposed COMPARATOR. Based on the Monte Carlo simulation, the offset voltage of this COMPARATOR is obtained 2.8mV.