Fluorenone has attracted significant interest in nanoelectronics due to its promising electronic properties. This study investigates the effects of an electric field on fluorenone to evaluate its suitability for nanoelectronic applications using density functional theory (DFT) and Landauer theory. The electronic properties of fluorenone, including the energy gap, dipole moment, electron spatial extent (ESE), cohesive energy, and current-voltage characteristics, were systematically analyzed under varying electric field strengths. Results show that while cohesive energy and bond lengths remain largely unaffected, the energy gap decreases significantly with increasing electric field strength. Additionally, the dipole moment and ESE distribution increase substantially. The current-voltage profile exhibits a sharp rise in current with increasing field intensity, underscoring fluorenone’s potential as a strong material for field-effect molecular devices, such as molecular wires. These findings highlight fluorenone’s sensitivity to external electric fields, supporting its viability for advancing nanoelectronic technologies. This study provides critical insights into the tunability of fluorenone’s electronic properties, paving the way for its integration into next-generation nanoscale electronic systems.

Extremely efficient successor and predecessor circuits are suggested in this article using 4 CNTFETs. They have much less interconnections and complexity compared to the best previous circuits. The proposed circuits are designed by combining digital and analog techniques for the first time. They can be expanded for all MVLs like ternary, quaternary, pentaternary, and so on. The proposed designs for quaternary logic reduce the transistor count from 25 to 4 in comparison with the best previous works. Interestingly, in MVLs with more level logics, this difference will increase dramatically. This advantage leads to low complexity and costs. The accurate operation and great performance of introduced circuits are illustrated and their superiority is proved. Additionally, a quaternary half adder is founded on the presented successor and predecessor. The simulation results, which are acquired by comprehensive simulations utilizing Synopsys HSPICE and the 32 nm plenary CNTFET model of Stanford, show that proposed successor and predecessor circuits with only four transistors work accurately. According to these outcomes, in the proposed half-adder, not only the transistor count reduces 32%, but also it has 40% better PDP and 42.05% better EDP in comparison with the best previous work. Also it is more stable against process variation and robust in a wide range of temperature variation.

Nowadays, the portable multimedia electronic devices, which employ signal-processing modules, require power aware structures more than ever. For the applications associating with human senses, approximate arithmetic circuits can be considered to improve performance and power efficiency. On the other hand, scaling has led to some limitations in performance of nanoscale circuits. Accordingly, Carbon Nanotube Field Effect Transistors have gotten a widespread attention as the most appropriate replacement for MOSFETs. In this paper, an imprecise full adder cell based on CNFET minority gates is introduced. Evaluation and comparison of the minority-based and the-state-of-the-art imprecise full adders in terms of average power dissipation, delay and power delay product (PDP) are done. The error distance (ED), normalized error distance (NED) and PDP-NED product metrics are also considered for assessing the accuracy of the reviewed circuits. The HSPICE simulations, conducted using Stanford 32nm CNFET model, indicate that the minority-based design outperforms the other designs in terms of performance and error tolerance.

A novel technique for creating logic gates and digital circuitry at the nanoscale is quantum cellular automata (QCA). The sensitivity of the circuit is enhanced and quantum circuits are more susceptible to unfavorable external conditions when component size are reduced. In this article, we offer a five-input majority gate with fault-tolerant feature in QCA technology, taking into account the significance of constructing circuits that can withstand flaws. We also assess all potential defects in the process of arranging cells in specific locations on the surface. These errors consist of extra cells, rotation, deletion, and displacement. The gate under study is subjected to the aforementioned four failure categories in the first stage. The QCADesigner simulator engine is then used to assess the accuracy of the circuit performance in the second step. 41 quantum cells have been used to make the gate of this five-input majority gate with fault-tolerant feature in QCA technology. Several techniques are explored to discover such a majority gate, such as adding cells (i.e., introducing redundancy into the circuit) and particular cell layout techniques. The goal is to come up with a design that can ideally withstand possible faults with the least amount of overhead on the circuit for fault-tolerant through a certain cell layout. The findings demonstrate the implemented majority gate's notable advantage over comparable scenarios.

Adders are among the most practical and useful circuits in microprocessors. They could also be used in other arithmetic operators. Traditionally, they are fabricated using CMOS technology. However, CMOS has faced some challenges in the nanoscale regime such as reduced gate controllability and high leakage currents. In contrast, Quantum Cellular Automata (QCA) is a promising alternative for the challenges of the next generation digital circuits. Based on QCA idea, in this paper a Carry-Skip Adder (CSA) is designed, which as far as investigated, has not been previously presented in related works. As CSA adders are generally faster than ripple ones, our simulation results also confirm that the proposed CSA outperforms the state-of-the-art ripple and carry lookahead adders and produces the result three QCA clock cycles faster even in the worst-case scenario. In addition, the proposed QCA adder outperforms its CMOS counterpart in terms of speed and power consumption.

Memristor is the forth fundamental circuit element that has received considerable attention due to its possible applications in future nanoscale systems. This paper describes the advantages that this nanoscale elements and nanotechnology may offer in the implementation of encryption algorithms in hardware and embedded platforms. To demonstrate this subject, , an Advanced Encryption Standard core was designed and implemented in both CMOS and hybrid CMOS/nanotechnology. The resistance of both implementation s against power analysis attack was evaluated and compared. It was demonstrated that hybrid CMOS/Nano circuit provides considerable improvement over implementation with regular CMOS circuits in terms of power consumption and resistance against Differential Power Analysis (DPA) attacks without needing to apply any costly algorithmic countermeasure or using any extra circuit. Simulations were carried out using HSPICE and Cadence Spectre and the attack algorithm was written in MATLAB. The results obtained in this paper can be used in enhancing the security of the future generation of urban and commercial smart information and communication systems.

Quantum-dot Cellular Automata (QCA) technology is a highly promising emerging technology that serves as a viable alternative to CMOS technology. On the other hand, the decoder is one of the vital building blocks in digital circuits. This paper presents and evaluates two novel 2:4 decoder circuits in QCA technology. The 2:4 decoder is a crucial component in digital systems, responsible for translating binary information from encoded input signals to a unique output signal. The first proposed circuit is implemented in a single layer, and the second proposed circuit is implemented in 3 layers. The functionality of the proposed decoder circuits is verified using the QCADesigner tool. The obtained results demonstrate that the designed coplanar QCA decoder has 34 cells, 0.02 , and 0.5 clock cycles delay. In addition, our proposed multilayer decoder has 34 cells, 0.01  area, and 0.5 clock cycle delay. The coplanar and multilayer developed decoder circuits have 2.08  and 2.33 , average Ebath energy, respectively. The comparison results indicate that the proposed circuits have advantages compared to other decoder circuits.

The aim of this paper is to suggest new and efficient designs for XOR circuits based on nanomagnetic logic technology in order to implementation of nanomagnetic computational circuits such as adders, subtractors and multipliers. Nanomagnetic logic due to its properties such as very high speed, low power consumption, scalability and working on room temperature is a suitable alternative for conventional transistor technology. First, nanomagnetic majority gates are introduced then two efficient designs with minimum area, minimum number of nanomagnetic elements and lowest delays for XOR circuits are proposed based on a three-input minority gate and a five-input majority gate. Basic elements in these designs are out-of-plane nanomagnetic cells made of Co/Pt, due to relative advantages of this alloy. Clocking field which is an external uniform magnetic field is required for proper performance of these proposed circuits. MagCAD tool was used for implementation of these designs, and the accuracy of operation of these circuits was proved by applying Modelsim simulator. According to the results of this simulation, it is shown that the proposed single layer and multilayer three-input XOR gates have improvement in comparison to the state-of-art design in number of gates 50% and 25%, in delay 80% and 80%, and in the number of elements 23% and 21%, respectively.

Due to the unique physical and chemical properties of two-dimensional (2D) materials, such as linear band structure near the Fermi level, high electrical and thermal conductivity, they have opened up a wide vision in the fabrication of nanoelectronic devices, energy storage and information transmission. One of the theses materials that has recently received attention is a two-dimensional monolayer of boron atoms called borophene which has various allotropes such as α, β12, χ3, 2-pmmn and 8-pmmn. This 2D material has tilted and anisotropic Dirac cone and in addition to excellent transparency, it has excellent electron and ion conductivity. These properties along with other properties of borophene have caused diverse and potential applications of this material in gas sensors, metal ion batteries and electronic and optoelectronic devices. In this paper, we intend to review the properties of borophene and investigate the effect of factors such as impurity, light radiation, strain, dimension reduction in the form of nanoribbon, temperature, electric and magnetic fields on the properties of electron transport in this material.

In this paper we propose a method to study the impact of the CNT parameter variations on performance of CNTFET digital circuits. In particular we consider CNT parameters that fully identify the geometrical properties of a regular CNT, which are the length and structural indices (n, m) of CNT. We analyse in particular the effects on NAND gate using a N and P type CNTFET, polarizing at a fixed voltage and varying the CNT parameters.  As regards the indices, we limit the analysis to zig-zag CNT, highlighting that the proposed procedure can be applied to other types of CNT.