Usually two-dimensional substitution is used for the production of integrated circuits. Due to heavy use of communications, two-dimensional substitution has high losses as well as, density of elements is low in it. To resolve this problem, three-dimensional substitution method was proposed. Rather than the two-dimensional arrangement of elements in a row, elements are layout in three dimensions in this substitution. In this paper, three-dimensional substitution algorithms using order used in two-dimensional substitution, three-dimensional substitution analysis by mPL and three-dimensional substitution simultaneous with two-dimensional substitution by mPL have been studied in terms of structure and function, and a butterfly processing element (PE) and an Advanced Encryption Standard (AES) block and a wireless MIMO decoder to assess them have been implemented with the mentioned methods. . Applying these methods shows that the use of face to face integration by microbuses in communications of substitution algorithm, on average, improves the maximum clock and block speed of AES encryption to 15. 3% and the maximum clock and block speed of PE module to 22. 6% as well as the maximum clock and speed of MIMO modules to 17. 1%, while the use of these methods has led to the average reduction in power consumption of 2. 6% for the AES module and the average reduction in power of 12. 9% for the PE module and the average reduction in power consumption of 5. 1% for MIMO module.

Quantum computing is a new method of information processing that is based on the concepts of quantum mechanics and leads to strange and powerful events in the quantum field. The LOGIC SYNTHESIS of quantum circuits refers to the process of converting a given quantum gate into a set of gates that can be implemented in quantum technologies. The most famous LOGIC SYNTHESIS methods are CSD and QSD. The main goal of this study is to present a multi-objective LOGICal SYNTHESIS method combining the above two methods in the quantum circuit model with the aim of optimizing the evaluation criteria. In this proposed method, the solution space is created from different combinations of CSD and QSD decomposition methods. The created solution space is a space with a very large exponential size. Then, using a bottom-up approach of multi-objective dynamic programming, a method is presented to search only a part of the entire solution space to find circuits with the optimal Pareto costs. The obtained results show that this method creates a balance between the evaluation criteria and produces many optimal Pareto solutions that can be selected according to different quantum technologies.

Knowing the components of economic education provides the dynamic background of education in this field. The aim of the current research is to investigate the indicators and components of the economic education curriculum. The approach of the current research is qualitative and its method is research SYNTHESIS. The research community is all the articles (211 articles) that have been presented from 1390 to 1401 AD and from 2010 to 2022 AD regarding economic education in curricula. The sample of the research is 32 articles, which were selected based on thematic monitoring, theoretical data saturation, and purposefully. The research data were collected from the qualitative analysis of the studied articles. By analyzing the data, the dimensions of vitality in the curriculum of the elementary school in 4 factors and 55 categories including the dimension of individual factors (including indicators and components related to personality characteristics); The dimension of culture and economic ethics (economic fields in the society); The dimension of economic concepts and knowledge (indices in economic education) and the dimension of collective and communication concepts (communication and interaction indicators in education) were classified. Economic education is dependent on internal and external components in educational systems, which requires macro-planning in this field.

Quantum-LOGIC SYNTHESIS refers to generating a quantum circuit for a given arbitrary quantum gate according to a specific universal gate library implementable in quantum technologies. Previously, an approach called block-based quantum decomposition (BQD) has been proposed to synthesize quantum circuits by using a combination of two well-known quantum circuit SYNTHESIS methods, namely, quantum Shannon decomposition (QSD) and cosine-sine decomposition (CSD). In this paper, an improved block-based quantum decomposition (IBQD) is proposed. IBQD is a parametric approach and explores a larger space than CSD, QSD, and BQD to obtain best results for various SYNTHESIS cost metrics. IBQD cost functions for SYNTHESIS are calculated in terms of different SYNTHESIS cost metrics with respect to the parameters of the proposed approach. Furthermore, in order to find optimum results according to these functions, IBQD SYNTHESIS approach is defined as a constrained-optimization model. The results show that IBQD can lead to the minimum total gate cost among all the proposed approaches for the specific case of 4-qubit quantum circuit SYNTHESIS. Moreover, for the first time, the depth costs of the CSD, QSD, BQD, and IBQD SYNTHESIS approaches are evaluated and it is shown that IBQD makes a trade-off between the total gates and depth costs for the synthesized quantum circuits.

Reversible LOGIC has been emerged as a promising computing paradigm to design low power circuits in recent years. The SYNTHESIS of reversible circuits is very different from that of non-reversible circuits. Many researchers are studying methods for synthesizing reversible combinational LOGIC. Some automated reversible LOGIC SYNTHESIS methods use optimization algorithms Optimization algorithms are used in some automated reversible LOGIC SYNTHESIS techniques. In these methods, the process of finding a circuit for a given function is a very time-consuming task, so it’, s better to design a processor which speeds up the process of SYNTHESIS. Application specific instruction set processors (ASIP) can benefit the advantages of both custom ASIC chips and general DSP chips. In this paper, a new architecture for automatic reversible LOGIC SYNTHESIS based on an Application Specific Instruction set Processors is presented. The essential purpose of the design was to provide the programmability with the specific necessary instructions for automated SYNTHESIS reversible. Our proposed processor that we referred to as ARASP is a 16-bit processor with a total of 47 instructions, which some specific instruction has been set for automated SYNTHESIS reversible circuits. ARASP is specialized for automated SYNTHESIS of reversible circuits using Genetic optimization algorithms. All major components of the design are comprehensively discussed within the processor core. The set of instructions is provided in the Register Transform Language completely. Afterward, the VHDL code is used to test the proposed architecture.