Background: Pregnancy is associated with structural and functional changes in the cardiovascular system as well as obesity, high blood triglyceride concentration, and increased risk of metabolic syndrome.Objective: The aim of this study was to compare parity between women with established coronary heart disease and normal women in general population.Materials and Methods: Totally, 105 women referred for coronary artery bypass grafting surgery during a period of more than one year were enrolled. Total fertility rate (TFR) was evaluated in this group of patients and we also compared TFR of these women with that of normal women.Results: Based on the results, 884 pregnancies were occurred in total of 105 patients (mean parity=8.34). There was a significant difference between the TFR of the CABG patients and the TFR of the normal women in 1966 (p value=0.038), the TFR of the normal women in the past 40 years (p value<0.001), the TFR of the normal women in province of Sistan and Baluchistan (p value<0.001).Conclusion: Our findings suggest that the number of pregnancy is an independent risk factor associated with coronary artery disease.

The objective of this paper is to investigate the dynamics of adjustment to long-run purchasing power parity (PPP)in a nonlinear framework using the Iranian data over the period 1959-2000. Two PPP measures are considered and nonlinearity in the real exchange rates are investigated. First, the standard and modified unit root tests are applied and then, cointegration analysis is carried out, based on the Johansen (1988) and Johansen and Juselius (1990) cointegration methodology, rather than imposing the strict cointegating vector in calculating real exchange rate measures. Furthermore, the Smooth transition autoregressive (STAR) representation for the adjustment process towards PPP, which provides a superior alternative, are specified and estimated. It was found that purchasing power parity (PPP) holds in the long-run after accounting for structural breaks. Moreover, linearity was strongly rejected and the dynamic STAR models were specified and estimated by using nonlinear least squares. The strong evidence in favour of nonlinear behaviour for PPP suggests that the linear models are misspecified.

Reversible logic is a new technology that is considered as an essential requirement for the design of quantum computers. In the calculation unit of computers, multiplication is one of the most frequently used operations. In this paper, we propose new optimized algorithms to design a parity-preserving reversible Vedic multiplier. Three approaches for designing optimized reversible Vedic multiplier circuits are proposed which are better than the existing circuits in terms of quantum cost, number of garbage outputs, number of constant inputs, and other criteria. The proposed reversible Vedic multipliers can be generalized to produce parity-preserving n*n reversible multiplier. We have also achieved some relations which can calculate the quantum cost, the number of constant inputs, and the number of required garbage outputs for the proposed Vedic circuit of any dimension. We have shown that our proposed reversible Vedic multiplier in n*n scale is the best compared to the existing Vedic multipliers.

Reversible logic is one of the new paradigms for power optimization that can be used instead of the current circuits. Moreover, the fault-tolerance capability in the form of error detection or error correction is a vital aspect for current processing systems. In this paper, as the mult iplication is an important operat ion in computing systems, some novel reversible multiplier designs are proposed with the paritypreserving property which will be useful for error detection. At first, two optimal signed serial multipliers are presented based on the Booth’ s algorithm and its enhanced version called the K-algorithm, ut ilizing the new arrangements of reversible gates. Then, another low-cost serial multiplier is proposed based on the conventional Add & Shift method to be ut ilized in the applications in which unsigned numbers are used. Finally, a new signed parallel multiplier is proposed based on the Baugh-Wooley method that is useful for speed-critical applications. The comparative results showed that the proposed mult ipliers are much bet ter than the existing designs regarding the main criterions used in reversible logic circuits including quantum cost, gate count, constant inputs, and garbage outputs.