IN THIS PAPER A CORDIC BASED APPLICATION-SPECIFIC INSTRUCTION-SET PROCESSOR (ASIP) FOR TWO DIMENSIONAL DISCRETE FOURIER TRANSFORM (DFT) AND DISCRETE COSINE TRANSFORM (DCT) IS PROPOSED. TODAY, DFT PERFORMS AN IMPORTANT ROLE IN DIGITAL SIGNAL PROCESSING, AND DCT ALGORITHM IS SUITABLE FOR IMAGE COMPRESSION APPLICATIONS. USING CORDIC METHOD INSIDE THESE TWO SIGNAL PROCESSING ALGORITHMS REDUCES THE NUMBER OF MEMORY ACCESSES. ASIP CAN ACT AS AN ALTERNATIVE TO ASIC AND GPP DESIGN IF IT DOES SATISFY THE CRITICAL POINTS OF POWER CONSUMPTION, TOTAL DELAY, MANUFACTURING COST AND PRODUCTIVITY OF THOSE DESIGNS. FURTHERMORE, FOR SATISFYING THESE PARAMETERS, TWO STAGE OF UTILIZATION IS PERFORMED ON THE BASIC MANO MODEL. AS A MATER OF FACT, TEMPORARY REGISTERS AND DATA BUS ARE IMPROVED, RAM AND CACHE MEMORY ARE ADDED, AND THE NUMBER OF FUNCTIONAL UNITS IS INCREASED. AS A RESULT THE NUMBER OF GATES IN THE CONTROL UNIT IS DECREASED ABOUT 84% IN THE DFT AND 86% IN THE DCT IN COMPARISON TO THE MANO DESIGN. MOREOVER, THE DFT AND THE DCT INSTRUCTIONS IN THIS DESIGN CONSUME 3.6% AND 3.86% AS THE NUMBER OF CLOCKS AS THE MANO DESIGN DOES. UTILIZATION IN THE PROPOSED PIPELINE ARCHITECTURE IS EVALUATED WITH REGISTER TRANSFER LANGUAGE (RTL) CODES.