Digital transformers are considered as one of the digital circuits being widely used in signal and data processing systems, audio and video processing, medical signal processing as well as telecommunication systems. Transforms such as Discrete Cosine Transform (DCT), Discrete Wavelet Transform (DWT) and Fast Fourier Transform (FFT) are among the ones being commonly used in this area. As an illustration, the DCT is employed in compressing the images. Moreover, the FFT can be utilized in separating the signal spectrum in signal processing systems as fast as possible. The DWT is used in separating the signal spectrum in a variety of applications from signal processing to telecommunication systems, as well. In order to build a VLSI circuit, several steps have to be taken from chip design to final construction. The first step in the synthesis of the integrated circuits is called high-level synthesis (HLS), in which a structural characteristic is obtained from a behavioral or algorithmic description. The resulting structural characteristic is equivalent to the one being considered in the behavioral description and it somehow represents the method for implementing the behavioral description as a result several structural descriptions could be implementable for each behavioral description. Therefore, depending on the intended use, the characteristic will be selected that outperforms the others. The main purpose of the HLS is to optimize the power consumption, the chip occupied area and delayed and is fulfilled by selecting the appropriate number of operating units and how they are implemented to the operators. This is generally accomplished through a graph analysis called the data flow graph (DFG) which is a graphical representation of the type and how the operators connect. In the DFG, each node is equivalent to an operator while the edges represent the relationship between these operators. Experience has proved that if the level of design optimization is high, in addition to higher efficiency, the design time will be lower, which is why the researchers are far more interested in optimization at higher levels of design than the lower levels. The complex, extensive, and discrete nature of the HLS problems have been ranked them among the most complex problems in VLSI circuits engineering. Bearing this mind, using meta-heuristic and Swarm intelligence methods to solve high-level synthesis projects seems to be a favored option. In this paper, a heuristic method called Moth-Flame Optimization (MFO) has been used to solve the HLS problem in the design of digital transformer to find the optimal response. The MFO is a population-based heuristic algorithm that optimizes the problems using the laws of nature. The leading notion behind the MFO algorithm inspired from the moths’ movements and their instinctive navigation during the night. In the MFO algorithm, the moths are like chromosomes in the GA and like the particles in the PSO algorithm. In order to compare and prove the efficiency of the proposed method, it was applied on the test data with the GA-based method separately but with the same initial conditions. The comparative results along with the results of the GA-based method demonstrated that the proposed method exhibits a higher ability to provide the appropriate hardware structure and high-level synthesis of various types of transformers. Another outstanding feature of the proposed method is its high speed of finding an optimal response with an average of more than 20% greater than the GA based method.

This paper proposes the efficient VLSI architecture of camera distortion correction, based on a Neural Camera Distortion Model (NCDM). Conventional imaging methods use over two kinds of models to correct the camera and lens distortions, but the NCDM uses a single model to immediately correct the geometry distortion and unsymmetrical manufacturing errors. The NCDM, with four neurons, performs a wide-angle distortion correction. The results show that the maximal corrected error in a whole image is less than 1.1705 pixels, and the MSE approaches 0.1743 between corrected and ideal results. The distortion correction by NCDM is 429more accurate than the conventional approach. The chip size of NCDM is 1: 51×1: 51 mm2 and contains 126 K gates using the TSMC 90 nm CMOS technology process. Working at 240 Mhz, this architecture can correct 30 frames and a Full-HD resolution video per second. Results show that the maximal corrected error in a whole image is less than 1.4 pixels, and the mean square error approaches 0.0376 between corrected and ideal results.

Image data require huge amounts of disk space and large bandwidths for transmission. Hence, image compression is necessary to reduce the amount of data required to represent a digital image. Therefore an efficient technique for image compression is highly pushed to demand. Although, lots of compression techniques are available, but the technique which is faster, memory efficient and simple, surely hits the user requirements. In this paper, the image compression, need of compression, its principles, how image data can be compressed, and the image compression techniques are reviewed and discussed. Also, wavelet-based image compression algorithm using Discrete Wavelet Transform (DWT) based on B-spline factorization technique is discussed in detail. Based on the review, some general ideas to choose the best compression algorithm for an image are recommended. Finally, applications and future scopes of image compression techniques are discussed considering its development on FPGA systems.

With the growing complexity of VLSI systems, automatic physical design of today's systems has become very complex. One approach to control overall complexity is to divide the design into several levels of hierarchy. This may produce poor results if the inter-dependence between various components of the design is not considered. In addition, the high degree of inter-dependence between design processes operating at the physical and higher levels of abstraction (e.g. the specification level) necessitates a number of iterations between these levels. One effective solution, exploited by this work, is the use of a common design hierarchy for both specification and physical level design. This can provide physical data to the specification level synthesis process, thereby reducing the design cycle. In this paper, a framework for the floorplanning and placement of macrocell designs is introduced. Inter-dependence between levels of a design specification hierarchy is taken into account in this framework. Since the framework is not inherently restricted by either the hierarchy depth or the hierarchy branching factor, it is able to preserve an arbitrary specification hierarchy. The framework gathers geometric information about the design over several traversals of the design specification hierarchy and sets the physical geometries, such as port positions, orientation, etc., in a stepwise refinement fashion. The results show that the framework produces good results quickly for large designs.  

Viterbi decoder is used for decoding data encoded using Convolution Forward Error Correction codes or data that suffers from inter-symbol interference. They occur in a large proportion of digital transmission. Viterbi decoders employed in digital wireless communications are complex and dissipate large power. The proposed method focuses on gate diffusion input (GDI) which is a low power technique of digital circuit design. Dynamic component of power is reduced in GDI technique as source of PMOS is not permanently connected to Vdd. It also reduces the latency of the circuit. The Viterbi decoder is implemented using GDI cell with 0.25 mm and 90 nm technology with 2.5 V Vdd. Frequency is varied from 15 MHz to 25 MHz. The outputs of the convolutional encoder designed for the constraint lengths K 4, 5, 6, 7 and rate are fed to the designed Viterbi decoder. The comparison results showed 29% reduction in power consumption and 66% reduction in area by using GDI circuit than the CMOS circuit.

An SPICE compatible model for multiple coupled nonuniform lossless transmission lines (TLs) is presented. The method of the modeling is based on the steplines approximation of the nonuniform TLs and quasi-TEM assumptions. Using steplines approximation the system of coupled nonuniform TLs is subdivided into arbitrary large number of coupled uniform lines (steplines) with different characteristics. Then using modal decomposition method the system of coupled partial differential equations for each step is decomposed to a number of uncoupled ordinary wave equations describing uncoupled uniform TLs in each step. To satisfy the boundary conditions at the discontinuities a new model is developed. Therefore each step of the system can be modeled in SPICE using a set of ideal delay lines representing uncoupled TLs and some linear-dependent voltage and current sources. Finally some examples are given to show the validity and usefulness of the model.

In this paper a very fast 4-2 compressor is introduced. Considering the fact that technological miniaturization is going to reach to its physical limits, there is no way except presenting new approaches and using new architectures. In this design we have improved the overall speed of the system using combined voltage and current mode circuits. All the simulation are done based on BSIMv3 and .25 urn technology. We have used Hspice and CosMos-Scope tools. The input patterns are generated and applied with MATLAB. According to the simulations, the proposed circuit has demonstrated significant improvement in terms of speed and power dissipation. The parameter used to compare the simulations reseals is PDP (power delay product). The other factor in order to compare these two designs is the number of transistors used. The proposed design illustrates 20% reduction in the transistor count.

Fabrication of an integrated circuit with smaller area, besides reducing the cost of manufacturing, usually causes a reduction in the power dissipation and propagation delay. Using the static CMOS technology to fabricate a circuit that realizes a specific logic function and occupies a minimum space, it must be implemented with continuous diffusion runs. Therefore, at the destine stage, an Eulerian path should be found for the logic function. Every discontinuity causes an increase in the area as well as a reduction in the clock rate and performance. The realization of a logic function using the static CMOS technology is done through different methods, most of which are based on the Uehara's method. In this paper, an algorithm is suggested that finds the Eulerian path and allows the implementation of the circuit with continuity in the diffusion region that results in minimum area. In a case where there is no Eulerian path, the possible sub-paths are found. In addition, the algorithm gives information that helps the layout generation.