Design and simulation results of fully integrated 5-GHz CMOS LNAs are presented in this paper. Three different input impedance matching techniques are considered. Using a simple L-C network, the parasitic input resistance of a MOSFET is converted to a 50Ω resistance. As it is analytically proven, that is because the former methods enhance the gain of the LNA by a factor that is inversely proportional to MOSFET’s input resistance. The effect of each input impedance matching on the amplifier’s noise figure and gain is discussed. By employing the folded cascode configuration, these LNAs can operate at a reduced supply voltage and thus LOWer POWER consumption. To address the issue of nonlinearity in design of LOW voltage LNAs, a new linearization technique is employed. As a result, the IIP3 is improved extensively without sacrificing other parameters. These LNAs consume 1.3 mW POWER under a 0.6 V supply voltage.

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Background and Aim Research has shown that social POWER affects information processing in many ways and can induce POWERful movements or gestures. This study aimed to investigate the effect of pretending POWER gestures on changing the pain threshold of a group of female students. Methods & Materials The method of the present study was quasi-experimental with a pre-test post-test design with a control group. The statistical population of this study included all female students of Arak University in the academic year 2016-2017, from which 60 people selected by convenience sampling method, and randomly divided into three groups: high POWER posing (sitting on a chair and putting your feet on the table, placing your hands behind your head and holding your head up), LOW POWER posing (sitting on a chair with your legs together, arms between your legs and bending your head to bottom) and control. Rosenberg self-esteem scale and tourniquet technique with cuff pressure gauge (to measure pain threshold) used to collect data. After the pre-test measurements and two minutes of gestures, the post-test was performed immediately. Data were analyzed using the analysis of covariance. Ethical Considerations This study was approved by the ethics committee of Arak University of Medical Sciences (Code: IR. ARAKMU. REC. 1399. 276). Results The results showed that pretending high/LOW POWER gesture significantly affects pain threshold,pretending to have a high-POWER gesture increases the pain threshold, and pretending to have a LOWPOWER gesture LOWers the pain threshold. Conclusion Based on the results, using POWER gestures as a simple tool in pain situations is recommended for pain management or as a supplement to analgesics.

In this paper, a novel LOW voltage LOW POWER current buffer was presented. The proposed structure was implemented in CMOS technology and is the second generation of OCB (orderly current buffer) called OCBII. This generation is arranged in single inputsingle output configuration and has modular structure. It is theoretically analyzed and the formulae of its most important parameters are derived. Pre and Post-layout plus Monte Carlo simulations were performed under  0. 75 V by Cadence using TSMC 0. 18 μ m CMOS technology parameters up to 3rd order. The proposed structure could expand and act as a dual output buffer in which the second output shows extremely high impedance because of its cascode configuration. The results prove that OCBII makes it possible to achieve very LOW values of input impedance under LOW supply voltages and LOW POWER dissipation. The most important parameters of 1st, 2nd and 3rd orders, i. e. input impedance (Rin),-3 dB bandwidth (BW), POWER dissipation (Pd) and output impedance (Ro) were found respectively in Pre-layout plus Monte Carlo results as: 1st order: Rin (52. 4 Ω ), BW (733. 7 MHz), Pd (225. 6 μ W), Ro (105. 6 kΩ ) 2nd order: Rin (3. 8 Ω ), BW (576. 4 MHz), Pd (307 μ W), Ro (106. 4 kΩ ) 3rd order: Rin (0. 34 Ω ), BW (566. 9 MHz), Pd (535. 6 μ W), Ro (118. 2 kΩ ) And in Post-layout plus Monte Carlo results as: 1st order: Rin (59. 9 Ω ), BW (609. 6 MHz), Pd (212. 4 μ W), Ro (106. 9 kΩ ) 2nd order: Rin (11. 3 Ω ), BW (529. 3 MHz), Pd (389. 9 μ W), Ro (109. 8 kΩ ) 3rd order: Rin (5. 8 Ω ), BW (526. 5 MHz), Pd (514. 5 μ W), Ro (125. 5 kΩ ) Corner cases simulation results are also provided indicating well PVT insensitivity advantage of the block.

Scaling challenges and limitations of conventional silicon transistors have led the designers to apply novel nano-technologies. One of the most promising and possible nano-technologies is CNT (Carbon Nanotube) based transistors. CNFET have emerged as the more practicable and promising alternative device compared to the other nanotechnologies. This technology has higher efficiency compared to the silicon-based MOSFET and is appropriate for high-frequency applications. Full Adder cell is the essential core and the building block of most arithmetic circuits and is placed on most parts of their critical paths. In this paper, POWER-efficient CNFET (Carbon Nanotube Field Effect Transistor) based Full Adder cell is proposed. This design is simulated in several supply voltages, frequencies and load capacitors using HSPICE circuit simulator. Considerable improvement is achieved in terms of POWER and PDP (POWER-Delay-Product) in comparison with other classical CNFET-based designs, in the literature. Our proposed Full Adder can also drive large load capacitance and works properly in LOW supply voltages.