In this paper, the routing architecture for an FPGA with hybrid clusters built from a mixture of LUT-based and PLA-like blocks is investigated. The implemented CAD flow that is used to place and route a number of MCNC benchmark circuits in a comparative fashion is discussed. The experimental results demonstrate that cluster sizes of two (2 LUT blocks and 2 PAL blocks) to four (4 LUT blocks and 4 PAL blocks) are appropriate in terms of area and speed. A comparison between hybrid and LUT-based FPGA architectures is also presented, showing that hybrid FPGA has some considerable advantages over a uniform LUT-based architecture.

This paper mainly focused on implementation of AES encryption and decryption standard AES-128. All the transformations of both Encryption and Decryption are simulated using an iterative design approach in order to minimize the hardware consumption. This method can make it a very low-complex architecture, especially in saving the hardware resource in implementing the AES InverseSub Bytes module and Inverse Mix columns module. As the S -box is implemented by look-up-table in this design, the chip area and power can still be optimized. The new Mix Column transformation improves the performance of the inverse cipher and also reduces the complexity of the system that supports the inverse cipher. As a result this transformation has relatively low relevant diffusion power. This allows for scaling of the architecture towards vulnerable portable and cost-sensitive communications devices in consumer and military applications.