In this paper, the routing architecture for an FPGA with hybrid clusters built from a mixture of LUT-based and PLA-like blocks is investigated. The implemented CAD flow that is used to place and route a number of MCNC benchmark circuits in a comparative fashion is discussed. The experimental results demonstrate that cluster sizes of two (2 LUT blocks and 2 PAL blocks) to four (4 LUT blocks and 4 PAL blocks) are appropriate in terms of area and speed. A comparison between hybrid and LUT-based FPGA architectures is also presented, showing that hybrid FPGA has some considerable advantages over a uniform LUT-based architecture.

Now days, sharing data in communication systems and computers require high levels of Information security. Side channel attack is one of the methods which it is applied to attack cryptographic systems such as smart cards. In this paper, a new approach for countermeasuring cryptographic algorithms has been proposed and implemented on FPGA. The scheme is based on using Phase Locked Loop in AES algorithm which by disturbing power consumption pattern and execution time of different rounds, the resistance of the algorithm against power attack has been increased. Masking and hiding technique has been used to protect the encryption key. Overall, the proposed method has been simulated within TSMC 65nm technology platform and outstanding success has been obtained; in applying the technique to AES, the overhead was 13% in CMOS area, 15% in power consumption, 2% decrease in working frequency while finding the key became difficult for attackers. In addition, the proposed method has been implemented on FPGA and satisfactory results have been obtained for an acceptable number of samples of the power trace.

There are di erent kinds of attacks on Field Programmable Gate Array (FPGA). As FPGAs are used in many di erent applications, its security becomes an important concern, especially in Internet of Things (IoT) applications. Hardware Trojan Horse (HTH) insertion is one of the major security threats that can be implemented in unused space of the FPGA. This unused space is unavoidable to meet the place and route requirements. In this paper, we introduce an e cient method to  ll this space and thus leaving no free space for inserting HTHs. Using a shift register in combination with gate-chain is the best way of  lling unused space, which incurs a no increase in power consumption of the main design. Experimental results of implementing a set of IWLS benchmarks on Xilinx Virtex devices show that the proposed prevention and detection scheme imposes a no power overhead and no degradation to performance and critical path delay of the main design.