An integrated CMOS, low-power optical communication receiver front-end is designed and presented in this paper for specified applications of 10Gbp/s. The transimpedance AMPLIFIER (TIA) stage and the limiting AMPLIFIER (LA) stage possess an active feedforward network based on CURRENT-mirror topologies and differential topologies, respectively. In order to obtain broadband performance, low-power consumption characteristic and low-occupied area on chip, an active type of inductors are employed in the TIA as well as the LA stage. The performance of the optical system is simulated using 90 Nano-meter CMOS technology parameters, which exhibits power dissipation of only 1. 5mW,-3dB frequency of 6. 92GHz, 24pA/√ Hz input referred noise, and transimpedance gain of 40. 1dB ohm for the TIA stage, while, the whole optical receiver front-end consumes 7. 7m Watt, providing 71. 4dB ohm gain beside acquiring 6. 55GHz frequency bandwidth. Finally, the performance of the presented optical receiver front-end as a low-power, 10Gbps block-diagram is justified.