Implantable image sensors have several biomedical applications due to their miniature size, light weight, and low power consumption achieved through sub-micron standard CMOS (Complementary Metal Oxide Semiconductor) technologies. The main applications are in specific cell labeling, neural activity detection, and biomedical imaging. In this paper the recent research studies on implantable CMOS image sensors for neural activity monitoring of brain are being quantified and reviewed. Based on the results, the suitable implantable image sensors for brain neural monitoring should have high signal to noise ratio of above 60 dB, high dynamic range of near 88 dB and low power consumption than the safety threshold of 4W/cm2. Moreover, it is found out that the next generation of implantable imaging device trend should reduce the pixel size and power consumption of CMOS image sensors to increase spatial resolution of sample images.

Fabrication of an integrated circuit with smaller area, besides reducing the cost of manufacturing, usually causes a reduction in the power dissipation and propagation delay. Using the static CMOS technology to fabricate a circuit that realizes a specific logic function and occupies a minimum space, it must be implemented with continuous diffusion runs. Therefore, at the destine stage, an Eulerian path should be found for the logic function. Every discontinuity causes an increase in the area as well as a reduction in the clock rate and performance. The realization of a logic function using the static CMOS technology is done through different methods, most of which are based on the Uehara's method. In this paper, an algorithm is suggested that finds the Eulerian path and allows the implementation of the circuit with continuity in the diffusion region that results in minimum area. In a case where there is no Eulerian path, the possible sub-paths are found. In addition, the algorithm gives information that helps the layout generation.

The main portion of the power consumption in high speed register files is related to read out paths which are implemented using the dynamic circuits. For this reason, a new dynamic circuit technique is proposed in this paper to reduce the power consumption of the register files without significant speed and noise immunity degradation. In the proposed dynamic circuit, the pull down network is partitioned to the some smaller pull down networks to increase the circuit performance. Moreover, pull-down networks are precharged using NMOS transistors to reduce the voltage swing and hence decrease the power consumption. A 64-word x 32-bit 2-read, 1-write ported register file is implemented using the proposed circuit technique. Simulation of register files are performed using HSPICE simulator in low-Vth 90-nm CMOS technology model. Simulation results demonstrate 37% and 36% reduction in power and delay respectively at the same noise immunity compared to the conventional register file.

In energy supply applications for low-power sensors, there are cases where energy should be transmitted from a low-power battery to an output stage load capacitor. This paper presents an adiabatic charging circuit with a parallel switches approach that connects to a low-power battery and charges the load capacitor using a buck converter which operates in continuous conduction mode (CCM). A gate controller of parallel switches (GCPS) is used to increase the duty-cycle of the input signal of buck converter switches, which controls the inductor current and charges the load capacitor in 256 steps. The proposed parallel switches approach is used to improve the energy efficiency under different powers transmission and comprises a current sensor, comparator, R-S latch, parallel pMOS switches, and parallel nMOS switches. For high powers transfer, the large switches are paralleled with small switches and result in conduction losses reduction. Also, for low powers transfer, the total switching losses are significantly reduced by turning off the large PMOS/NMOS switches during the charging operation. The proposed circuit was designed and simulated in a 0.18μm CMOS technology. The efficiency of the proposed circuit during the capacitor charge-up cycle is more than 80% for average input powers between 0.5mW to 30mW.

With the increasing complexity of integrated circuits, the cost of testing is on the rise. Design for testability methodologies with the introduction of extra hardware tries to reduce different cost factors associated with the testing of a complex circuit at the expense of added chip area.In this paper, a novel universal gate is proposed for the complete testability of combinational circuits. Also, an algorithm is devised to perform the simple testing of sequential circuits. The ease of testing, using the proposed structure is independent of the size and complexity of the circuit. Two different designs using CMOS technology are proposed.