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Title

A NOVEL SCHEME FOR FAULT-TOLERANT AND HIGHER CAPACITY NETWORK ON CHIP

Pages

 Start Page 45 | End Page 51

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Abstract

 As CMOS technology scales down, NoC (Network on Chip) gradually becomes the mainstream of on-chip communication. In this paper we present a methodology to design fault-tolerant routing algorithms for regular direct interconnection networks. It supports fully adaptive routing, does not degrade performance in the absence of faults, and supports a reasonably large number of faults without significantly degrading performance. Consequently, this work examines fault tolerant communication algorithms for use in the Communication Networks including NoC domain. Before two different flooding algorithms, a random walk algorithm and an Intermediate Node Algorithm have been investigated. The first three algorithms have an exceedingly high communication overhead and cause huge congestion in usual traffics. The fourth one which is Intermediate Node algorithm is a static fault-tolerant algorithm which focuses on the faults knowing in advance where they are located. We have developed a new dynamic algorithm based on intermediate node concept and stress value concept to overcome all of blind sides of mentioned algorithms. We have designed a switch/router base on this algorithm and simulated by MAX PLUS II tool and verified it on a mesh NoC in Xilinx environment.

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