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Information Journal Paper

Title

Switched-Capacitor Dynamic Threshold PMOS (SCDTPMOS) Transistor for High Speed Sub-threshold Applications

Author(s)

 ASHRAF M. | Issue Writer Certificate 

Pages

  170-177

Abstract

 This work studies the effects of Dynamic Threshold design techniques on the speed and power of digital circuits. A new Dynamic Threshold transistor structure has been proposed to improve performances of digital circuits. The proposed switched-capacitor Dynamic Threshold PMOS (SC-DTPMOS) scheme employs a capacitor along with an NMOS switch in order to effectively reduce the threshold voltage of a PMOS transistor. The proposed structure improves the propagation delay of a circuit and is much suitable for those circuits with high switching factor. Post layout simulation results using TSMC 180 nm CMOS technology at 0. 2V supply voltage shows 45% improvement in delay as well as 25% less power consumption at the cost of only 53% more occupied area.

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    • Cite

    APA: Copy

    ASHRAF, M.. (2018). Switched-Capacitor Dynamic Threshold PMOS (SCDTPMOS) Transistor for High Speed Sub-threshold Applications. IRANIAN JOURNAL OF ELECTRICAL AND ELECTRONIC ENGINEERING, 14(2), 170-177. SID. https://sid.ir/paper/299949/en

    Vancouver: Copy

    ASHRAF M.. Switched-Capacitor Dynamic Threshold PMOS (SCDTPMOS) Transistor for High Speed Sub-threshold Applications. IRANIAN JOURNAL OF ELECTRICAL AND ELECTRONIC ENGINEERING[Internet]. 2018;14(2):170-177. Available from: https://sid.ir/paper/299949/en

    IEEE: Copy

    M. ASHRAF, “Switched-Capacitor Dynamic Threshold PMOS (SCDTPMOS) Transistor for High Speed Sub-threshold Applications,” IRANIAN JOURNAL OF ELECTRICAL AND ELECTRONIC ENGINEERING, vol. 14, no. 2, pp. 170–177, 2018, [Online]. Available: https://sid.ir/paper/299949/en

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