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Title

A 1 V UWB LNA WITH EXCELLENT GROUP DELAY VARIATION

Writers

HAZERI A.R.

Pages

 Start Page 120 | End Page 123

Abstract

 In this paper, a 1 V UWB LNA in TSMC 0.13 um CMOS process technology is designed. The power consumption is only 7.6 mW. By employing RLC peaking, high-frequency poles are moved outside of the 3.1-10.6 GHz band of interest, and a flat power gain and an excellent phase linearity are achieved. By applying DC voltage to the bulk of transistors, a LOW VOLTAGE LNA is accomplished. The proposed LNA is consisted of two stages and uses only 2 inductors. The proposed LNA has the power gain of 8.7  ~ 10.3, low NF of 3.5 ~ 4.2 dB, IIP3 of -6 dB, and good input return loss greater than -17 dB. The -3 dB bandwidth of S21 is from 0.6 to 13 GHz.

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