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Paper Information

Journal:   JOURNAL OF ADVANCES IN COMPUTER ENGINEERING AND TECHNOLOGY   spring 2018 , Volume 4 , Number 2 (serial 14); Page(s) 61 To 68.

Cost-aware Topology Customization of Meshbased Networks-on-Chip

Author(s):  Ramezanzad Ali*, RESHADI MIDIA
* Department of Computer Engineering , Science and Research Azad University Tehran, Iran
The small world network idea recently has been introduced in order to optimize the performance of the Networks-on-chip. Based on this method the architecture will be neither fully customized nor completely regular. Results have shown that by using the longrange links which optimized the network power and performance, the area consumption will exceed. We can derive from this that an acceptable bound on the area consumption should be considered. Based on the restriction of a designer, in this paper we want to present a methodology that will automatically optimize an architecture while at the same time considering the area consumption.
Keyword(s): Networks-on-chip,long-range link insertion,power and area consumption,average latency
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