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Paper Information

Journal:   JOURNAL OF SOFT COMPUTING AND INFORMATION TECHNOLOGY (JSCIT)   SPRING 2016 , Volume 6 , Number 1 ; Page(s) 1 To 7.
 
Paper: 

FAULT-TOLERANT 3-D NETWORK-ON-CHIP DESIGN USING DYNAMIC LINK SHARING

 
 
Author(s):  SEYYEDAGHAEI REZAEI SEYYED HOSSEIN*, MODARRESSI MEHDI
 
* DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING, COLLEGE OF ENGINEERING, UNIVERSITY OF TEHRAN, TEHRAN, IRAN
 
Abstract: 

Emerging 3D technology partitions a larger die into smaller parts and then stacks them in a 3D fashion. This technology can lead to a paradigm shift in on-chip communication design providing higher orders of bandwidth and lower latency. However, due to the aggressively scaled transistors in modern technology nodes, the reliability issue has become into a major concern. In this paper,we leverage these ultra-low-latency vertical links to design a fault-tolerant 3D NoC architecture. In this architecture, permanent and intermittent defects on links and crossbars are bypassed by borrowing the idle bandwidth from vertically adjacent links and crossbars. Evaluation results under synthetic and realistic workloads show that the proposed fault-tolerance mechanism offers higher reliability and lower performance loss, when compared with state-of-the-art fault-tolerant 3D NoC designs.

 
Keyword(s): FAULT-TOLERANT, RESOURCE SHARING, 3-D NOCS
 
 
References: 
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Click to Cite.
APA: Copy

SEYYEDAGHAEI REZAEI, S., & MODARRESSI, M. (2016). FAULT-TOLERANT 3-D NETWORK-ON-CHIP DESIGN USING DYNAMIC LINK SHARING. JOURNAL OF SOFT COMPUTING AND INFORMATION TECHNOLOGY (JSCIT), 6(1 ), 1-7. https://www.sid.ir/en/journal/ViewPaper.aspx?id=569142



Vancouver: Copy

SEYYEDAGHAEI REZAEI SEYYED HOSSEIN, MODARRESSI MEHDI. FAULT-TOLERANT 3-D NETWORK-ON-CHIP DESIGN USING DYNAMIC LINK SHARING. JOURNAL OF SOFT COMPUTING AND INFORMATION TECHNOLOGY (JSCIT). 2016 [cited 2021May12];6(1 ):1-7. Available from: https://www.sid.ir/en/journal/ViewPaper.aspx?id=569142



IEEE: Copy

SEYYEDAGHAEI REZAEI, S., MODARRESSI, M., 2016. FAULT-TOLERANT 3-D NETWORK-ON-CHIP DESIGN USING DYNAMIC LINK SHARING. JOURNAL OF SOFT COMPUTING AND INFORMATION TECHNOLOGY (JSCIT), [online] 6(1 ), pp.1-7. Available: https://www.sid.ir/en/journal/ViewPaper.aspx?id=569142.



 
 
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