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Paper Information

Journal:   SCIENTIA IRANICA   2014 , Volume 21 , Number 3 (TRANSACTIONS D: COMPUTER SCIENCE AND ENGINEERING AND ELECTRICAL ENGINEERING); Page(s) 826 To 841.
 
Paper: 

HIGH SPEED MULTIPLIER USING HIGH ACCURACY OATING POINT LOGARITHMIC NUMBER SYSTEM

 
 
Author(s):  SAHA P., BANERJEE A., DANDAPAT A., BHATTACHARYYA P.*
 
* DEPARTMENT OF ELECTRONICS AND TELECOMMUNICATION ENGINEERING, BENGAL ENGINEERING AND SCIENCE UNIVERSITY, SHIBPUR, HOWRAH-711103, INDIA
 
Abstract: 

ASIC implementation of a high speed multiplier using a high accuracy oating point logarithmic number system is reported in this paper. The most popularly used techniques for computing logarithmic calculations for digital signal processors are: Lookup table based implementation, polynomial approximation, and Taylor series expansion. But, all these techniques suer from low accuracy, due to the choice of having only lower order terms of the expanded series. In the present work, logarithmic conversion is implemented by a oating point (IEEE-754 single precision) converting methodology, thereby eliminating series expansion, which eventually results in high accuracy. The improvement in speed, by avoidance of carry propagation, was achieved through Canonical Signed Digit Code (CSDC) implementation, while the high accuracy was achieved through an error minimization circuitry especially designed for this purpose. The functionality of these circuits was checked, and performance parameters, like propagation delay and dynamic power consumption, were calculated by spice spectre using 90 nm CMOS technology. The propagation delay and power consumption of the resulting (128 128) bit multiplier (divider) was only 93 ns and ~ 80 mW, respectively, for a layout area of ~ 25mm2. This implementation oered a signi can’t improvement in terms of accuracy, delay and power from those reported earlier.

 
Keyword(s): CANONICAL SIGN DIGIT CODE, LOGARITHMIC NUMBER SYSTEM, MULTIPLIER, HIGH SPEED, HIGH ACCURACY
 
 
References: 
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Click to Cite.
APA: Copy

SAHA, P., & BANERJEE, A., & DANDAPAT, A., & BHATTACHARYYA, P. (2014). HIGH SPEED MULTIPLIER USING HIGH ACCURACY OATING POINT LOGARITHMIC NUMBER SYSTEM. SCIENTIA IRANICA, 21(3 (TRANSACTIONS D: COMPUTER SCIENCE AND ENGINEERING AND ELECTRICAL ENGINEERING)), 826-841. https://www.sid.ir/en/journal/ViewPaper.aspx?id=405797



Vancouver: Copy

SAHA P., BANERJEE A., DANDAPAT A., BHATTACHARYYA P.. HIGH SPEED MULTIPLIER USING HIGH ACCURACY OATING POINT LOGARITHMIC NUMBER SYSTEM. SCIENTIA IRANICA. 2014 [cited 2021May14];21(3 (TRANSACTIONS D: COMPUTER SCIENCE AND ENGINEERING AND ELECTRICAL ENGINEERING)):826-841. Available from: https://www.sid.ir/en/journal/ViewPaper.aspx?id=405797



IEEE: Copy

SAHA, P., BANERJEE, A., DANDAPAT, A., BHATTACHARYYA, P., 2014. HIGH SPEED MULTIPLIER USING HIGH ACCURACY OATING POINT LOGARITHMIC NUMBER SYSTEM. SCIENTIA IRANICA, [online] 21(3 (TRANSACTIONS D: COMPUTER SCIENCE AND ENGINEERING AND ELECTRICAL ENGINEERING)), pp.826-841. Available: https://www.sid.ir/en/journal/ViewPaper.aspx?id=405797.



 
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