Paper Information

Journal:   SCIENTIA IRANICA   MARCH- APRIL 2008 , Volume 15 , Number 2; Page(s) 231 To 237.
 
Paper: 

A PROGRAMMABLE GPS RECEIVER WITH TEST CIRCUITS IN 0.18 MOU M CMOS

 
 
Author(s):  RIAHI N.*, JENABI M., FOTOVAT AHMADI A.
 
* DEPARTMENT OF ENGINEERING, ALZAHRA UNIVERSITY, VANAK, TEHRAN, I.R. IRAN
 
Abstract: 

A 0.18 mm single chip GPS receiver, with 19.5 mA current consumption, is implemented in 6.5 mm2. Low-IF architecture was used for a high level of integration and low power consumption. A serial input digital control, with additional testing structure, not adding more than 4% to the Si area, is used in the actual RF circuits, in case of problems, minimizing the number of Si runs.

 
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