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Paper Information

Journal:   MODARES TECHNICAL AND ENGINEERING   WINTER 2007 , Volume - , Number 26 (SPECIAL ISSUE ON ELECTRICAL ENGINEERING); Page(s) 75 To 84.
 
Paper: 

RESEARCH NOTE: DESIGNING A RECONFIGURABLE ACCELERATOR

 
 
Author(s):  SEPYANI A.A.R., KABIR E.A.*, BEHAZIN F.
 
* DEPARTMENT OF ELECTRICAL ENGINEERING, TARBIAT MODARES UNIVERSITY, THEHRAN, IRAN
 
Abstract: 

Many of the video processing algorithms cannot be implemented in real time on general computers, due to their computational complexity. For an efficient implementation, a custom hardware that can be reconfigured for the algorithm, is used. In this paper a new acceleration hardware based on FPGA elements is proposed. This hardware can be adapted with the processing algorithm through FPGA design reconfiguration. Using a PCI slot, this hardware communicates with a Pc. The FPGAs are programmed through the PCI slot. The video frames are supplied to this hardware for processing. The performance of this hardware is evaluated using warping algorithms. The first and second order warping for a 512*512 frame can be done in 7.9 ms.

 
Keyword(s): ACCELERATOR, FPGA, REAL-TIME IMPLEMENTATION, IMAGE WARPING
 
References: 
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