Click for new scientific resources and news about Corona[COVID-19]

Paper Information

Journal:   NASHRIYYAH -I MUHANDISI -I BARQ VA MUHANDISI -I KAMPYUTAR -I IRAN, A- MUHANDISI -I BARQ   FALL 2018 , Volume 16 , Number 3 ; Page(s) 213 To 220.
 
Paper: 

Design Of Parity Preserving Reversible Signed Multiplier Circuit

 
 
Author(s):  Haghparast M.*, Bolhassani A.
 
* COMP. ENG. DEPT., SHAHR EREY AZAD UNIVERSITY, SHAHR E REY, I. R. IRAN
 
Abstract: 
One of the major challenges and constraints in designing very large integrated circuits is the power dissipation of transistors. Reversible logic is one of the new paradigm in reducing the power consumption of digital circuits in the quantum computing field. In this paper, an improved design of a parallel 5-bit parity preserving reversible signed multiplier circuit is presented. Reversible circuit designs with parity preserving property are an important issue for the implementation of fault tolerant systems in nanotechnology area. To design of the proposed multiplier, the reversible full adder circuit using 5×5 reversible HBF block with low quantum cost, and the 4×4 reversible HBL gate, with parity preserving property are proposed. The structure of the multiplier circuit consists of two parts of the partial product generation (PPG) and multi-operand addition (MOA). This structure is based on Baugh-Wooley and Wallace-Tree algorithms, which results in improved speed of operation in a 5-bit multiplier for signed digits. The proposed circuits are optimized based on important evaluation issues such as quantum cost, garbage outputs and constant inputs, and also are compared with the existing circuits. The main goal is to reduce the quantum cost, the number of constant inputs and garbage outputs in the design of the proposed multiplier circuit. The results of the final evaluation and comparison shows that the proposed multiplier in this study is improved by 26% in quantum cost, 9% in garbage outputs and 9% in constant inputs relative to the best existing designs.
 
Keyword(s): QUANTUM COMPUTING, REVERSIBLE CIRCUIT, SIGNED MULTIPLIER, PARITY PRESERVING, NANOTECHNOLOGY
 
 
International related papers: 
 
Most related Highly related Moderately related Least related
 
References: 
  • Not Registered.
  •  
  •  
 
Citations: 
  • Not Registered.
 
+ Click to Cite.
APA: Copy

HAGHPARAST, M., & BOLHASSANI, A. (2018). DESIGN OF PARITY PRESERVING REVERSIBLE SIGNED MULTIPLIER CIRCUIT. NASHRIYYAH -I MUHANDISI -I BARQ VA MUHANDISI -I KAMPYUTAR -I IRAN, A- MUHANDISI -I BARQ, 16(3 ), 213-220. https://www.sid.ir/en/journal/ViewPaper.aspx?id=611019



Vancouver: Copy

HAGHPARAST M., BOLHASSANI A.. DESIGN OF PARITY PRESERVING REVERSIBLE SIGNED MULTIPLIER CIRCUIT. NASHRIYYAH -I MUHANDISI -I BARQ VA MUHANDISI -I KAMPYUTAR -I IRAN, A- MUHANDISI -I BARQ. 2018 [cited 2022January25];16(3 ):213-220. Available from: https://www.sid.ir/en/journal/ViewPaper.aspx?id=611019



IEEE: Copy

HAGHPARAST, M., BOLHASSANI, A., 2018. DESIGN OF PARITY PRESERVING REVERSIBLE SIGNED MULTIPLIER CIRCUIT. NASHRIYYAH -I MUHANDISI -I BARQ VA MUHANDISI -I KAMPYUTAR -I IRAN, A- MUHANDISI -I BARQ, [online] 16(3 ), pp.213-220. Available: https://www.sid.ir/en/journal/ViewPaper.aspx?id=611019.



 
 
Persian Abstract Yearly Visit 100
 
 
Latest on Blog
Enter SID Blog