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Paper Information

Journal:   MAJLESI JOURNAL OF ELECTRICAL ENGINEERING   DECEMBER 2009 , Volume 3 , Number 4 (11); Page(s) 69 To 74.
 
Paper: 

A NOVEL CMOS RIPPLE COMPARATOR CELL USING THE GATE- DIFFUSION INPUT TECHNIQUE

 
 
Author(s):  KIANI SARKALEH A., POURAHANGARYAN F., NIARAKI ASLI R.
 
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Abstract: 

In this paper a new implementation of CMOS ripple comparator cell using the Gate-Diffusion Input (GDI) technique is presented. The proposed design using this technique allows for the reduction of power consumption, propagation delay, and the area of digital circuits while maintaining low complexity of logical design. The performance comparison with standard CMOS and GDI logic design techniques is presented. These methods are compared with respect to the number of devices, PDP, and power dissipation. Simulation results confirm that the proposed cell can work at low supply voltage and dissipates low power.

 
Keyword(s): RIPPLE COMPARATOR, PROPAGATION DELAY, LOW-POWER, PDP, GDI
 
 
References: 
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Citations: 
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APA: Copy

KIANI SARKALEH, A., & POURAHANGARYAN, F., & NIARAKI ASLI, R. (2009). A NOVEL CMOS RIPPLE COMPARATOR CELL USING THE GATE- DIFFUSION INPUT TECHNIQUE. MAJLESI JOURNAL OF ELECTRICAL ENGINEERING, 3(4 (11)), 69-74. https://www.sid.ir/en/journal/ViewPaper.aspx?id=198462



Vancouver: Copy

KIANI SARKALEH A., POURAHANGARYAN F., NIARAKI ASLI R.. A NOVEL CMOS RIPPLE COMPARATOR CELL USING THE GATE- DIFFUSION INPUT TECHNIQUE. MAJLESI JOURNAL OF ELECTRICAL ENGINEERING. 2009 [cited 2021October25];3(4 (11)):69-74. Available from: https://www.sid.ir/en/journal/ViewPaper.aspx?id=198462



IEEE: Copy

KIANI SARKALEH, A., POURAHANGARYAN, F., NIARAKI ASLI, R., 2009. A NOVEL CMOS RIPPLE COMPARATOR CELL USING THE GATE- DIFFUSION INPUT TECHNIQUE. MAJLESI JOURNAL OF ELECTRICAL ENGINEERING, [online] 3(4 (11)), pp.69-74. Available: https://www.sid.ir/en/journal/ViewPaper.aspx?id=198462.



 
 
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